Insanity is running the same simulink model over and over again and expecting a different result. That’s insanity - That guy from Farcry… Probably. Introduction At my job, we’re working on an opt...
Introduction & Context In the previous posts, we designed an entire custom ITCH parser, going all the way from raw ethernet parsing to having a market state. The overall functional block diag...
Introduction & Context In the previous posts, we designed an ITCH parser. ITCH 5.0 is the Nasdaq protocol that streams live market events to whoever has the licence to listen. We were able to...
Introduction & Context In the previous posts, we designed an ITCH parser. ITCH 5.0 is the Nasdaq protocol that streams live market events to whoever has the licence to listen. To build our par...
Introduction In the last post I presented you the basics of an ITCH Parser FSM and we stopped when we had a basic parser able to parse a premade ‘A’ order and commit basic state changes (even thou...
Introduction In the last post I presented the ITCH protocol which is Nasdaq’s way to broadcast live market data to trading systems. We also designed a simple MoldUDP64 parser, MoldUDP64 being the...
Introduction I’d say I’m a normal guy, but I’ve always liked very stupid projects. You may not know it but I have a decent interest in finance. So today we are exploring how FPGAs are used to pro...
Certified 100% No AI Slop Context & Channel Creation I don’t really plan youtube videos, I plan projects to leran nerw stuff. At first I did youtube videos as a resume thing. And I always t...
youtube video Introduction Github link to code : https://github.com/0BAB1/simple-ethernet I’d say I’m a normal guy, but I’ve always liked very stupid projects. So I made a CPU, the HOLY CO...
youtube video Introduction I always knew I had a gap in electronis. Before geting into FPGAs and ASIC deisgn, I was a mechanics enthusiats for most of my teenage years, thus my 1st degree in mec...
Introduction Long story short, I made a CPU, the HOLY CORE. It is pretty simple yet pretty mature. Github Link Docs At some point, I wanted to take the whole thing a step further, as I imp...
This post is not technical but rather a way for me to share thoughts on the HOLY CORE project. For context, HOLY CORE is an open source RV32I compliant CPU that runs on FPGA and the entire developm...
Using cocotb to test basic design and AXI interface In the fast paced digital landscape, Cocotb is a testbench framework that allows blablabla… If you are here you already know what cocotb is and...
Using Real Time (RT) Analysis to Compute Worker Occuption on a Production Line When it comes to starting a new project in a manufacturing company, determining the costs to come up with a quote is ...
Manual inference : A “bonus” sub-tutorial This post is a follow up to the “python to FPGA tutorial” . It covers the necessary process to manually implement the output IP from FINN in a design u...
Python to FPGA video : Kickstart your FPGA AI Projects Based on this video. This is a “DIY” tutorial derived from my 9 hours course. As I cannot teach all the different concepts here, you’ll ...
Learn how to implement AXI DMA on Zynq FPGA with a hands-on FFT example. Full Vivado & Vitis walkthrough: hardware design, bare-metal firmware, and AXI Stream interfacing.
Building your own AXI LED IP Based on this video. Level : Beginner in fpga (See prerequisites below). The repo containing HW & SW code Intro So you decided you want to learn more abou...