fpga 15
- MATLAB/Vivado HDL Cosimulation: Full Setup Guide & First Simulation
- FPGA HFT Order Book: Part 6, Hash Table XOR Folding for Order References
- FPGA HFT Order Book: Part 5, Price Ladder Implementation on FPGA
- FPGA HFT Order Book: Part 4, Order Tracking in BRAM
- FPGA HFT Order Book: Part 3, Verifying ITCH 5.0 Parser with cocotb
- FPGA HFT Order Book: Part 2, NASDAQ ITCH 5.0 FSM Parser
- FPGA HFT Order Book: Part 1, MoldUDP64 Parser in SystemVerilog
- Gigabit Ethernet MAC on FPGA: RGMII, AXI Stream & RISC-V Softcore on KC705 (HOLY CORE)
- Running DOOM on a Homemade CPU (HOLY CORE)
- HOLY CORE : My Biggest project - THOUGHTS
- Cocotb : Project Setup, AXI Verification & Workflow
- Pytorch AI on FPGA - FINN & VIVADO Tutorial P2
- Pytorch AI on FPGA - FINN Worflow Tutorial P1
- Direct Memory Access (DMA): A Hands on Zynq Example
- Zynq Custom IP (AXI LED) Workflow Overview - Vivado/Vitis Tutorial