Archives
- 28 May MATLAB/Vivado HDL Cosimulation: Full Setup Guide & First Simulation
- 12 Apr FPGA HFT Order Book: Part 6, Hash Table XOR Folding for Order References
- 11 Apr FPGA HFT Order Book: Part 5, Price Ladder Implementation on FPGA
- 08 Apr FPGA HFT Order Book: Part 4, Order Tracking in BRAM
- 02 Apr FPGA HFT Order Book: Part 3, Verifying ITCH 5.0 Parser with cocotb
- 01 Apr FPGA HFT Order Book: Part 2, NASDAQ ITCH 5.0 FSM Parser
- 31 Mar FPGA HFT Order Book: Part 1, MoldUDP64 Parser in SystemVerilog
- 30 Mar Editing Youtube Videos is Hard - THOUGHTS
- 30 Mar Gigabit Ethernet MAC on FPGA: RGMII, AXI Stream & RISC-V Softcore on KC705 (HOLY CORE)
- 01 Mar Programming a MSPM0 Custom PCB using an STLINK - PHILS LAB Complementary Tutorial
- 26 Jan Running DOOM on a Homemade CPU (HOLY CORE)
- 21 Nov Cocotb : Project Setup, AXI Verification & Workflow
- 05 Nov Real Time Analysis & Industrial Planning
- 26 Oct Pytorch AI on FPGA - FINN & VIVADO Tutorial P2
- 25 Oct Pytorch AI on FPGA - FINN Worflow Tutorial P1
- 21 Jul Direct Memory Access (DMA): A Hands on Zynq Example
- 16 Jul Zynq Custom IP (AXI LED) Workflow Overview - Vivado/Vitis Tutorial